1. Field
The present disclosure pertains to the field of data processing, and more particularly, to the field of error mitigation in data processing apparatuses.
2. Description of Related Art
As improvements in integrated circuit manufacturing technologies continue to provide for smaller dimensions and lower operating voltages in microprocessors and other data processing apparatuses, makers and users of these devices are becoming increasingly concerned with the phenomenon of soft errors. Soft errors arise when alpha particles and high-energy neutrons strike integrated circuits and alter the charges stored on the circuit nodes. If the charge alteration is sufficiently large, the voltage on a node may be changed from a level that represents one logic state to a level that represents a different logic state, in which case the information stored on that node becomes corrupted. Generally, soft error rates increase as circuit dimensions decrease, because the likelihood that a striking particle will hit a voltage node increases when circuit density increases. Likewise, as operating voltages decrease, the difference between the voltage levels that represent different logic states decreases, so less energy is needed to alter the logic states on circuit nodes and more soft errors arise.
Blocking the particles that cause soft errors is extremely difficult, so data processing apparatuses often include support for error correcting codes (“ECC”), parity, or other techniques for detecting, and sometimes correcting, soft errors. Depending on the particular technique used, and the extent to which it is implemented, the cost of this support may be additional hardware and reduced performance, and the level of detection or correction capability may be limited to one or two bit errors. Alternative error mitigation techniques, which may offer different cost and capability options to designers of data processing apparatuses, may be desired.